1. Field of the Invention
The invention relates to semiconductor packages, and in particular, to leadframe semiconductor packages mounted on a heat-sink and fabrication thereof.
2. Description of the Related Art
Requirements for faster signal transmissions are being driven by consumer demand for electronic devices with greater bandwidth capacity. Two main semiconductor packaging challenges encountered with high-speed data transmissions are: 1) thermal problems due to greater power consumption requirements; and 2) electrical problems due to higher signal bandwidth. In order to solve signal and power integrity (F3dB=0.35/tr) and heat dissipation (P=CL×f×VDD2) issues, semiconductor packaging with both lower parasitic effects and lower costs are required for high speed integrated circuit applications.
Conventional semiconductor quad flat packages (QFPs) are used for low cost applications. The low cost applications require improved power dissipation benefit from the use of drop-in heat sink (DHS), die pad heat sink (DPH), exposed drop-in heat sink (EDHS), or exposed pad low profile in QFP (E-PAD LQFP), respectively. However, letting the heat sink act as a ground plane or floating ground plane does not improve the electrical performance effectively.
FIGS. 1A-1D are cross sections of traditional quad flat packages with different heat sinks enhancing thermal performance. Referring to FIG. 1A, a drop-in heat sink quad flat package (DHS-QFP) 100a comprises a semiconductor die 110 attached on a die pad 125 with an adhesion 120 therebetween. The die pad 125 is mounted on a heat sink 130. The semiconductor die 110 electrically connects leads 150 through bonding wires 140. An encapsulation 160 encloses the semiconductor die 110, the die pad 125, the heat sink 130 and wire bonding between the semiconductor chip and leads.
Alternatively, the semiconductor die 110 can be directly mounted on the heat sink 130 with adhesion 120. The heat sink 130 can also serve as a die pad. Both ends of the heat sink 130 are connected to the lead 150 through the polyimide tape 135, as shown in the die pad heat sink quad flat pack (DPH-QFP) 100b in FIG. 1B. However, the problem, of this type designed is that electrical performance can not be improved with the heat sink acting as a floating plane.
Referring to FIG. 1C, a bottom surface 132 of the heat sink 130 can be exposed to the outer environment as an exposed drop-in heat sink quad flat pack (EHDS-QFP) 110c. The heat sink 130 can be integrated with the leadframe to meet low profile requirements as shown in an exposed pad low profile quad flat pack (E-PAD LQFP) 100d in FIG. 1D. E-PAD LQFPs are ideal for a wide range of devices, such as microprocessors, controllers, DSPs, high speed logic, FPGAs, PLDs, and ASICs. Applications include laptops, telecom devices, high end audio/video devices and CPU/GUI boards. Electrical performances can be improved with the bottom surfaces of the heat sink acting as a ground plane.
U.S. Pat. Nos. 6,326,678 and 6,552,417, the entirety of which is hereby incorporated by reference, disclose molded plastic packages with heat sinks and enhanced electrical performance. FIG. 2A is a cross section of a conventional EDHS-QFP package. As shown in FIG. 2A, a semiconductor die 211 is attached by a film of thermally conductive epoxy 210 to a thick copper heat sink 201. An annular ceramic ring 206 is attached by a dielectric adhesive 213 onto the heat sink 201 on one surface of a ceramic ring 206 and onto a lead frame 205 on an opposite surface of the ceramic ring 206. Package 200 forms a transmission line for each lead in the lead frame 205, with the heat sink 201 acting as a ground plane. In addition, lead frame 205 includes an interposer ring 208 which surrounds a semiconductor die 211 inside the window 212 of a ceramic ring 206. Interposer ring 208 is separated into four sections 208a-208d to allow independent connections to the power and ground terminals.
FIG. 2B is a 3D view of package 200 with the plastic molding 204 removed to clearly show the lead frame 205 and the interposer ring 208. The interposer ring sections 208a-208d are attached to the heat sink 201 with dielectric adhesive 213. Interposer ring sections 208a-208d are further supported by tie bars 241a-241d, which are embedded in plastic molding 204. Lead frame 205 is severed to provide electrically isolated leads 250. Each of the interposer ring sections 208a-208d is wire bonded to one of the leads 250. Further, interposer ring sections 241b and 241d, which are dedicated for connections to a ground terminal, are electrically connected to heat sink 201 via electrically conductive epoxy 240. Alternatively, spot welding or other suitable mechanism can be used to electrically connect interposer ring sections 208b and 208d to heat sink 201. Interposer ring 208 is designed to surround semiconductor die 211 in close proximity without being in contact with semiconductor die 211. Consequently, very short wire bonds to both semiconductor die 211 and leads 250 are possible. Such wire bonds have low inductance, which, in turn, reduces the parasitic impedances of package 200, thereby enhancing package 200's electrical performance. Because the interposer ring sections are internal to package 200 and are accessed readily for connections, the number of leads on lead frame 205 required for power and ground connections is reduced, thereby effectively increasing the available lead count of package 200. However, the drawback of the semiconductor packages 200 is that lead inductance is very large thereby detrimental to power integrity.
Taiwan Patent No. 1249829, the entirety of which is hereby incorporated by reference, discloses leadframe based semiconductor packages and fabrication methods thereof. An embedded and/or exposed heat sink is disposed between the chip and the leads to promote electrical and thermal performance.
FIG. 3 is a cross section of a conventional chip-on heat sink leadframe package. Referring to FIG. 3, a chip on heat sink, COHS-LF package 300 includes a chip 330 attached with adhesive 342 on a leadframe 336 integrated with a heat sink 360 structure. The leadframe 336 is defined with inner leads 362 and outer leads 364. Dielectric layer 344 is interposed between the leadframe 336 and the heat sink 360. Bond pads 332 of the chip 330 are electrically connected to the inner leads 362 through the bonding wires 334. An encapsulation 338 encloses the chip 330, the heat sink 360 and wire bonding 334 between the chip and inner leads 362. After the heat sink 360 is attached to the front side of a chip 330, the leadframe package is grounded to improve heat dissipation and to control impedance of the leads. The drawback of the COHS-LF package 300 is that it is not compatible to a standard leadframe packaging processes and the heat sink only acts as a ground net.
Thus, a novel semiconductor packing processes is desired, which is capable of fulfilling both high performance and low production costs for applications related to high speed product integration requirements such as using the system in package (SiP) to integrate RF+BB chips or DTV+DDR SDRAMs.